Conventional semiconductor flash cells (see FIGS. 1A and 1B) have a very low coupling ratio between the control gate of polycrystalline silicon (poly 2) and the floating gate of polycrystalline silicon (poly 1). The coupling ratio is defined as C.sub.2 /(C.sub.1 +C.sub.2) where C.sub.1 is the capacitance between the floating gate and substrate of the semiconductor device, and C.sub.2 is the capacitance between the control gate and the floating gate. Performance parameters of the flash cell are unnecessarily degraded by having such a low coupling ratio. It is therefore important to develop a method and article of manufacture to increase the coupling ratio. Further, conventional flash cells usually have a tungsten silicide seam formed which creates substantial degradation of electrical performance.